This invention relates to a bipolar transistor, and more particularly to a mesa bipolar transistor provided with a base layer formed by patterning semiconductor layers laminated by epitaxial growth; and an emitter layer.
In order to enhance operating speed of a bipolar transistor, the maximum cut-off frequency of the bipolar transistor (hereinafter referred to as fTmax) must be raised by narrowing the base width. If the base width is narrowed, however, the emitter-collector withstand voltage is lowered and punch-through occurs easily. To prevent this while the fTmax value is increased, therefore, the bipolar transistor must be provided with a base layer in which impurities are diffused densely and shallowly. Generally, for such the base layer, an impurity diffusion layer has been used. The diffusion layer is formed by implanting impurities in it with the ion implantation method. Ion implantation cannot make the impurity diffusion layer shallow because of channeling. For the bipolar transistor having a base layer formed such way, the upper limit of fTmax was 30 to 40 GHz.
To solve this problem, another bipolar transistor was proposed. The transistor used a base layer comprising a semiconductor layer formed by epitaxial growth. This bipolar transistor is formed as described below.
At first, as shown in FIG. 1A, a P-type impurity-contained silicon film is epitaxial-grown as a first semiconductor layer 12 on a substrate 11 having an N-type collector layer 11a formed on the surface. Then, on the surface of the first semiconductor layer 12 is epitaxial-grown an N-type impurity-contained silicon film as second semiconductor layer 13. After this, as shown in FIG. 1B, a resist pattern 901 is used as a mask for etching the second semiconductor layer 13 to form an emitter layer 13a comprising the second semiconductor 13. Then, the resist pattern 901 is removed and a resist pattern 902 is used as a mask for etching the first semiconductor layer 12 as shown in FIG. 1C to form a base layer 12a comprising the first semiconductor layer 12 under the emitter layer 13a. Subsequently, as shown in FIG. 1D, an insulating film 18 is formed on the substrate 11 so that the film may cover both emitter layer 13a and base layer 12a. Then, contact holes 18a are formed in the insulating film 18 so that the holes 18a may reach the collector layer 11a, the base layer 12a, and the emitter layer 13a, respectively. Finally, a wiring 19 is formed so that the wire may be connected to each of the above layers.
Compared with the transistor whose base layer is formed by ion implantation, a bipolar transistor 9 formed in such way is provided with a base layer 12a in which impurities are diffused more densely and shallowly. It is reported that the fTmax can be reached to around 50 GHz in this case.
The base layer 12a may also be formed by patterning the first semiconductor comprising an impurity-contained Si--Ge (silicon-germanium: SiGex) film. Compared with the bipolar transistor formed only with silicon, the hetero bipolar transistor having such a base layer 12a has a narrower base band gap, so the emitter density can be set lower. This is why both hFE drop caused by band gap narrowing and emitter-base withstand voltage drop can be prevented. In the hetero bipolar transistor in such a configuration, it is reported that fTmax can reach around 100 GHz.
In recent years, semiconductors are highly integrated and their functions are enhanced rapidly. Also in the data communication field, smaller communication devices and higher communication speed are demanded more and more accordingly. To achieve such demands, it is necessary to form the elements that can operate as fast (fTmax=120 GHz) as those formed with Ga--As (gallium-arsentic) on the object silicon substrate and package those elements in an IC. Making each of the above mentioned bipolar transistors practicable is thus strongly desired.
However, the following problems had to be solved to put such a bipolar transistor to practical use.
In other words, as shown in FIG. 1B, the above mentioned emitter layer 13a was patterned on the first semiconductor layer 12 used as a base layer. This is why when patterning the emitter 13a, over-etching of the base layer (first semiconductor layer 12) exposed out of the emitter layer 13a cannot be avoided. Consequently, as shown in FIG. 1C, in the base layer 12a, the film of the base region other than the intrinsic base region B just under the emitter layer 13a, that is, the external base region A, becomes thinner than that of the base region B and this makes the base resistance higher.
Increasing of the base resistance caused by this over-etching becomes more apparent when the base layer is thinner. This prevents the IC elements from being operated with high speed.